1. Technical Field
The present invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a recess gate in a semiconductor device.
2. Description of the Related Art
As semiconductor devices become highly integrated, transistor channel lengths are correspondingly shortened. Due to the shortening of the channel length, a short channel effect abruptly lowers threshold voltages more seriously in a conventional planar transistor.
In addition, an electric field of a substrate becomes very high due to the excessive ion implantation as memory devices such as a dynamic random access memory (DRAM) become increasingly integrated. In particular, a junction leakage current increases at a junction of a storage node contact SNC, which leads to a limitation of reduction of data retention time.
In order to overcome this limitation, a recess gate process has been widely used in recent years, by which a silicon substrate is recessed to a certain depth and a cell transistor of DRAM is then formed. As a result, the junction leakage current is reduced, increasing the data retention time.
FIGS. 1A and 1B illustrate a conventional method for manufacturing a recess gate. FIG. 1C illustrates an overlay misalignment between an active region and a recess pattern, and FIG. 1D illustrates a resultant structure after forming a gate insulating layer and a gate electrode. In FIGS. 1A to 1D, top diagrams are plan views and bottom diagrams are sectional views taken along line I-I′ of the top diagrams.
Referring to FIG. 1A, a field oxide layer 12 is formed on a substrate 11 using a shallow trench isolation (STI) process, defining an active region 13. Referring to FIG. 1B, a recess mask 14 having a straight line pattern with spacing therebetween is formed over the resultant structure. Active region 13 of substrate 11 is dry-etched to a certain depth using recess mask 14 as an etch barrier, thereby forming a recess pattern R. However, due to imperfect etch selectivity between active region 13 and field oxide layer 12, a portion of, field oxide layer 12 is inevitably recessed, denoted in FIG. 1B, while etching active region 13 to form a recess pattern R.
A recessed portion F of field oxide layer 12 is expanded and enlarged even more while field oxide layer 12, undergoes various cleaning processes using hydrofluoric acid (HF) based solution, whereby the reliability of the device is degraded. In addition, if there exists an overlay misalignment M (see FIG. 1C) between active region 13 and recess pattern R, a portion of active region 12 is undesirably etched (see R′ in FIG. 1C). That is, active region 13 is physically damaged due to overlay-misalignment M. Thus, in order to prevent physical damage to active region 13, an accurate overlay between active region 13 and recess pattern R must be achieved to prevent the deterioration of device characteristics.
FIG. 1D illustrates a resultant structure after forming a gate insulating layer 15 and a gate electrode 16. Here, a gate passing over recess pattern R is referred to as a recess gate, and a portion of the recess gate passing over field oxide layer 13 is referred to as a passing gate. By performing the recess gate process, a channel length increases due to recess pattern R, and thus the recess pattern is also called a recess channel.
The gate passing over recessed portion F of field oxide layer 12, i.e., a passing gate P, has an effect on a storage node SN of the adjacent active region so as to deteriorate the device characteristics, e.g., data retention time. As the field oxide layer, over which passing gate P passes, is damaged, i.e., the recessed portion of field oxide layer 13 is deepened, and the device characteristic is deteriorated.
The limitation caused by the passing gate as described above also exists in a bulb-shaped recess gate which has been proposed recently to maximize advantages of the recess gate process. When a misalignment occurs while recessing the bulb-shaped recess gate, an active region around a field oxide layer, i.e., a region where the storage node will be formed, is eventually damaged.